There are a large number and variety of basic fabrication steps used in the production of modern semiconductor devices. In order to fabricate a circuit consisting of thousands of components on a single silicon substrate, the movement of electrons is critical to the proper functioning of each device according to specified design rules. The production of electrons and associated holes enhancing the electrical characteristics of an given semiconductor device fabricated on the surface of a silicon wafer can be further enhanced by introducing controlled quantities of impurities or doping material. Doping elements such as phosphorus, arsenic, and antimony create n-type substrates while doping elements such as boron, indium, gallium, or aluminum create p-type substrates. Free electrons will move from a n-type substrate to a p-type substrate created by the doping process.
A limitation in the electrical characteristics of a device arises when doped polysilicon is deposited by chemical vapor deposition over a layer of silicon substrate. This process is used in forming a silicon gate. While the electrical devices created from the deposition of the doped polysilicon such a high impedance devices or local interconnects allow for conduction of electrons the dopant material from the polysilicon layer will migrate into an adjoining layer. Any migration of dopant material will ultimately change the electrical characteristics of the devices such as the resistance value of the high impedance device, determined by the dimension of the high impedance device, and the dopant level within the region creating the high impedance device. The fabrication of one type of semiconductor device, an electrical conductive contact and associated interconnect layers is described in US Patent Application Ser. No. 502,526 filed Mar. 30, 1990 to Nicholls et. al and entitled "Semiconductor Devices and Fabrication Thereof." A method of fabricating an insulating layer of silicon dioxide as part of an overall process of fabricating conductive or semiconductive layers to form a contact is described in U.S. Pat. No. 4,877,483 issued Oct. 31, 1989 to Bergemont et. al.
Another limitation arises where a layer of aluminum is deposited by chemical vapor deposition over a silicon substrate. Junction spiking results when aluminum atoms pass through the underlying silicon substrate into the layer beneath the silicon substrate. This junction spiking causes a hole and disrupts the junction between the silicon substrate and the layer beneath the silicon substrate resulting in a short circuit condition.
A further limitation arises where a dielectric or insulator exists between a doped polysilicon or aluminum layer and the underlying silicon substrate. A dielectric may provide enough resistance to prevent tunneling of electrons through the dielectric to or from the doped polysilicon or aluminum layer and into or out of the underlying silicon substrate. Tunneling of electrons does occur, however, where the dielectric is thin enough to allow current to flow across the dielectric. Tunneling currents are discussed in the IEEE Transaction On Electron Devices, Vol. 37, No. Aug. 8, 1990 in an article entitled "Thickness Limitation of SiO.sub.2 Gate Dielectrics for MOS ULSI"; in S. Pantelides, Physics Of SiO.sub.2 And Its Interfaces, (1978) in an article by M. Av-Ron, et. al at pp. 47-51 entitled "The Nature Of Electron Tunneling In SiO.sub.2 "; and, in R. Muller, T. Kamis, Device Electronics For Integrated Circuits, Section 3.4 "Junction Breakdown" (1977). The electrical properties of silicon nitride as taught in the present invention are discussed in general in the 1987 ECS Symposium Proceeding entitled "Silicon Nitride And Silicon Dioxide Thin Insulating Films" in an article entitled "Electrical Properties Of Thin LPCVD Si.sub.3 N.sub.4 Films On Mono-And Polycrystalline Silicon."